This invention relates to a data processing system comprising a main memory, a central processing unit, and a channel unit, which are all connected to a data bus and, in particular, to a data processing system for use in accessing the main memory from each of the central processing unit and the channel unit.
A virtual or logical address method is often adopted in a data processing system when a main memory is used in common to a plurality of programs and a memory capacity of the main memory is smaller than a capacity necessary for all of the programs. With the virtual address method, a virtual address should be converted or translated into a real address specifying each of physical addresses of the main memory when the main memory is accessed by each of a central processing unit and a channel unit.
It is preferable that such address translation is made as fast as possible. In particular, the address translation should proceed faster on an access from the central processing unit than on an access from the channel unit.
A conventional data processing system is provided with an address translating table memorized in a main memory to translate each virtual address into a real address. With the conventional system, address translation is possible without an increase of superfluous hardware. However, the main memory should be accessed to look up the address translating table each time when the address translation becomes necessary. Therefore, overhead time extremely becomes long for the address translation. This means that the address translating table can not be substantially utilized by the central processing unit because of a long overhead time. At any rate, the conventional data processing system inevitably brings about degradation of system performance.
In U.S. Pat. No. 3,902,163, issued to G. M. Amdahl et al and assigned to Amdahl Corporation, a data processing system is described which comprises a storage control section coupled to a central processing unit. The storage control section comprises a primary buffer memory for storing an address translation table transferred from a main memory. Such a buffer memory may generally be called a Table Lookaside Buffer (usually abbreviated to TLB in the art) and is operable at a high speed in comparison with the main memory. With the Amdahl system, address translation can rapidly be made by the use of the primary buffer memory when the central processing unit accesses the main memory. However, no suggestion is offered as to address translation of a logical address given from a channel unit. Therefore, such address translation slowly proceeds by accessing an address translating table stored in the main memory as mentioned before.
In order to carry out rapid address translation related to the channel unit, another buffer memory should be incorporated in the channel unit so as to store an additional address translation table which is identical with the address translation table stored in the primary buffer memory incorporated in the central processing unit. This, however, results in an increase of hardware. Inasmuch as both of the primary and the additional buffer memories must always be coincident in their contents with each other, superfluous hardware should also be added to the primary and the additional buffer memories as peripheral circuits.